ADC Clock Jitter Measurement Based on Simple Coherent Sampling Algorithm
نویسندگان
چکیده
Abstract In a high-speed sampling system, the clock jitter of analog-to-digital converters (ADCs) will greatly affect its accuracy, leading to reduction signal-to-noise ratio (SNR) system output. Therefore, it is necessary compensate results reduce error caused by measuring distribution sequence jitter. this paper, influence on ADC process analyzed, and an measurement scheme based simple coherent algorithm investigated. This can accurately measure jitter, has characteristics low computational complexity high precision. The simulation show that with root-mean-square (RMS) greater than 5ps when amplitude noise input signal 35dB, relative less 5%.
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ژورنال
عنوان ژورنال: Journal of physics
سال: 2022
ISSN: ['0022-3700', '1747-3721', '0368-3508', '1747-3713']
DOI: https://doi.org/10.1088/1742-6596/2366/1/012045